FPGA Design

Sidebranch actively develops FPGA logic designs and IP cores and develops firmware, software and Windows, Linux, and RTOS device drivers to support FPGAs in heterogenous CPU/SoC/FPGA designs.

Recent implementations we delivered:

• JPEG-LS loss-less image encoder. JPEG-LS uses very low FPGA resources and is one of the best loss-less algorithms, on par with the much bulkier JPEG-2000 in lossless mode. Our implementation encodes a pixel colour sample on each clock cycle, up to 4K and beyond, up to 16-bits per pixel. Many parallel instances where used on an Arria V GZ in a professional mobile application for panoramic street views.
• PCI Express Low-Latency SGDMA IP core. For this customer application it was tuned for offloading latency and throughput sensitive encryption tasks on an Arria V GX. Achieves down to 1.5 microseconds packet round-trip from CPU to FPGA back to CPU on 8 lanes PCI Express per packet, and handles millions of packets per second.

Besides the IP cores, we integrated this into the customer designs and developed Linux device drivers.